(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating salicide and self-aligned contact processes in the fabrication of integrated circuits.
(2) Description of the Invention
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In the production of memory units, the self-aligned contact (SAC) has been widely used to reduce cell size, thus greatly increasing the device density for the CMOS product design. With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates comprise several circuit functions on a single chip. For example, memory devices are formed on the same chip as the logic circuits which address them. It is desired to find a method of integrating the salicide and the SAC processes on one wafer so that both high logic performance and high density memory for embedded memory can be achieved.
The standard SAC process needs to use an insulator-capped polysilicon. This makes the process incompatible with the salicide process.
Silicidation has been widely used in the art. Silicidation techniques and self-aligned contacts are discussed in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 144-149 and in ULSI Technology, by C. Y. Chang and S. M. Sze, McGraw-Hill, New York, N.Y., c. 1996, pp.397-402 and 487-488. U.S. Pat. No. 5,573,980 to Yoo shows a method of forming a salicided SAC for an SRAM, but with no embedded logic. U.S. Pat. Nos. 5,605,853 and 5,719,079, both to Yoo et al teach formation of a 4T SRAM and floating gate memory and logic device including salicide and a butted contact, but not including a SAC.